This invention relates in general to binary up/down (U/D) counters. More specifically, the present invention provides specific circuits for up/down binary counters that are particularly well suited for CMOS integration.
Up/down counters are now well known and have become standard "building blocks" used by digital design engineers. They have a wide range of application in various digital devices, such as, for example, communication equipment. Traditional circuit implementations for U/D counters require large amounts of logic gates to produce the desired up or down count function. For example, referring to FIG. 1 (prior art) there is shown a known circuit implementation for an "off-the-shelf" binary counter. The binary counter shown in circuit is a Texas Instruments SN54S169 or SN74S169.
For many applications, it is not terribly significant how many logic gates are needed to implement a binary counter circuit. In this particular example, the Nth stage requires an input NAND gate having N-1 inputs, an N input NOR gate and N- AND gates.
In the particular example shown in FIG. 1 (PRIOR ART) four stages (stage #1 . . . stage #4) of binary counter are illustrated. Stage #4 requires a three input NAND gate 10, four AND gates 14 and a four input NOR gate 12. As can be seen from the illustrated arrangement a substantial number of gates are required for implementing the U/D counter.
Although the FIG. 1 (PRIOR ART) circuit arrangement may be quite suitable for many types of integration, such as for example TTL and others, it is not suitable for CMOS integrations because of the large number of logic gates required.